/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2012-2020.
 * Description: The C union definition file for the module PPE_TNL_0_8
 * Author: yanbo
 * Create: 2012-12-25
 */
#ifndef GMAC_PPE_REG_H
#define GMAC_PPE_REG_H

/* Define the union bus_ctrl */
/* PPE_CFG_BUS_CTRL is bus control register */
/* 0x424 */
union bus_ctrl {
	/* Define the struct bits */
	struct {
		/* [ 31..24 ] are reserved. */
		unsigned int reserved_1 : 8;
		/* [ 23 ] When accessing the DDR,pkt indicator is valid. */
		unsigned int cf_rw_ddr_bus_pkt_ind : 1;
		/* [ 22..21 ] 00: Read sending Disabled read_invalid;
		 * 01: If a descriptor address push released cache is 0 (rel released cache),
		 * enable read_invalid, otherwise, is disabled Other values:
		 * Transmit Descriptor enable read_invalid.
		 */
		unsigned int cf_tx_rd_bd_invalid : 2;
		/* [ 20..17 ] DDR write outstanding depth, max is 15 and the minimum configuration is 1. */
		unsigned int cf_wr_ddr_outstanding : 4;
		/* [ 16..13 ] outstanding depth when reading DDR packets,
		 * max TNL0-1 is 12,TNL2-8 is set to 4, the minimum configuration is 1
		 */
		unsigned int cf_rd_ddr_outstanding : 4;
		/* [ 12 ] send buffer to be released is released directly to the local computer. */
		unsigned int cf_local_rel_buf : 1;
		/* [ 11..9 ] Write POE outstanding depth, max TNL0-1 is 7,TNL2-8 is set to 4,
		 * the minimum configuration is 1
		 */
		unsigned int cf_wr_poe_outstanding : 3;
		/* [ 8 ] The POE fails (VMID fails or Telepresence full cache shielding function is released. */
		unsigned int cf_rx_add_poe_fail_rel_buf_msk : 1;
		/* Working descriptor write enable  [ 7 ]: 0: not write POE;1: POE. */
		unsigned int cf_we_enable : 1;
		/* [ 6 ] packet descriptors and write cache the packet header length:
		 * 0: all packets using cf_alloc_num_def value as write cache length;
		 * 1: According to the packet length type is written to the cache.
		 */
		unsigned int cf_rx_calloc_mode : 1;
		/* [ 5..1 ] packet descriptors and packet header
		 * write cache line total number(allocated by the number of cache)
		 */
		unsigned int cf_alloc_num_def : 5;
		/* [ 0 ] write descriptor endian configuration: 0: Little endian. 1: Big endian. */
		unsigned int cf_bd_endian : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union rx_ctrl */
/* PPE_CFG_RX_CTRL is an RX control register. */
/* 0x428 */
union rx_ctrl {
	/* Define the struct bits */
	struct {
		/* [ 31..13 ] are reserved. */
		unsigned int reserved_14 : 19;
		/* [ 12..7 ] stores the received packets,
		 * the packet header to the cacheline aligned address offset bytes.
		 */
		unsigned int cf_rx_align_num : 6;
		/* [ 6..0 ] corresponds to ADD POE source device number Node_Code, must be set to 0x7F. */
		unsigned int cf_node_code : 7;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union rx_max_frame_len */
/* Overlong MAX_FRAME_LEN to receive frame threshold register. */
/* 0x500 */
union rx_max_frame_len {
	/* Define the struct bits */
	struct {
		/* [ 31..14 ] cannot be configured. */
		unsigned int reserved_21 : 18;
		/* [ 13..0 ] received long frame threshold register. */
		unsigned int max_frame_len : 14;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union rx_pkt_mode */
/* PPE_CFG_RX_PKT_MODE input mode.  to receive packets */
/* 0x504 */
union rx_pkt_mode {
	/* Define the struct bits */
	struct {
		/* [ 31 ] are reserved. */
		unsigned int reserved_22 : 1;
		/* [ 30..25 ] input packets skip bytes, this area does not performs protocol parsing. */
		unsigned int cf_l2_skip1 : 6;
		/* [ 24..20 ] input packets skip bytes, this area does not performs protocol parsing. */
		unsigned int cf_l2_skip2 : 5;
		/* [ 19..18 ] Packet Mode: 00: not parse. */
		unsigned int cf_parse_mode : 2;
		/* [ 17..7 ] reserved */
		unsigned int reserved_23 : 11;
		/* [ 6..0 ] Ethernet packet header type distance offset. */
		unsigned int eth_offset : 7;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union MC_PPE_CFG_QOS_GRP_VMID_GEN_U */
/* PPE_CFG_QOS_GRP_VMID_GEN is QOS, GRP, VMID generation mode register. */
/* 0x520 */
union cfg_qos_grp_vmid_gen  {
	/* Define the struct bits */
	struct {
		/* [ 31..17 ] are reserved. */
		unsigned int reserved_27 : 15;
		/* [16] VMID mode: 0: Parse generates. */
		unsigned int vmid_mode : 1;
		/* [15] grp mode: 0: Parse generates. */
		unsigned int grp_mode : 1;
		/* [14] QOS mode: 0: Parse generates. */
		unsigned int qos_mode : 1;
		/* [ 13..10 ] VMID value by default. */
		unsigned int def_vmid : 4;
		/* [ 9..4 ] grp value by default. */
		unsigned int def_grp : 6;
		/* [ 3..0 ] qos value by default. */
		unsigned int def_qos : 4;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union rx_buffer_size
 * PPE_CFG_RX_BUFF_FIFO_RX_BUF_SIZE is buffer FIFO buffer size configuration register.
 * FIFO_0~FIFO_31 the  0x0400~0x047C are cache size configuration register
 * 0x0400 + pool_num * 0x4
 */
union rx_buffer_size {
	/* Define the struct bits */
	struct {
		/* [ 31..25 ] are reserved. */
		unsigned int reserved_16 : 7;
		/* [ 24..23 ] bound to this pool buf type (The K is not accurate values,
		 * only indicates the buf size type):00:1K;01:2K;10:4K;11:8K.
		 */
		unsigned int cf_buf_type : 2;
		/* [ 22..20 ] are reserved. */
		unsigned int reserved_17 : 3;
		/* [ 19 ] according to the QoS packet loss enable. */
		unsigned int qos_drop_en : 1;
		/* [ 18 ] Application BMU receive buffer address enable. */
		unsigned int cf_rx_cfg_req_en : 1;
		/* [ 17..14 ] packet non-initial buf skip2 in cache line size. */
		unsigned int cf_rx_no_frt_skip2 : 4;
		/* [ 13..10 ] header buf skip2 in cache line size. */
		unsigned int cf_rx_frt_skip2 : 4;
		/* [ 9..0 ] The buf available in cache line size. */
		unsigned int cf_rx_buf_size : 10;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union rx_fifo_size_cfg
 * PPE_CFG_RX_BUFF_FIFO_SIZE buffer FIFO size configuration register.
 * FIFO_0~FIFO_31 0x0500~0x057C are cache size configuration register
 * 0x0500 + pool_num * 0x4
 */
union rx_fifo_size_cfg {
	/* Define the struct bits */
	struct {
		/* [ 31..28 ] are reserved. */
		unsigned int reserved_18 : 4;
		/* [ 27..16 ] buffer for storing address FIFO depth */
		unsigned int cf_depth : 12;
		/* [ 15..12 ] VMID of the pool. */
		unsigned int cf_vmid : 4;
		/* [ 11 ] cache address of each pool mode: 0: LIFO. */
		unsigned int cf_fifo_en : 1;
		/* [10..0] FIFO start address (the fifo usage from cf_start_addr to cf_start_addr+cf_depth-1,
		 * so pay attention to a FIFO cf_start_add> a FIFO cf_start_addr+ before a FIFO cf_depth-1)
		 */
		unsigned int cf_start_addr : 11;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union tx_des_addr */
/* PPE_CFG_TX_PKT_BUF_ADDR is a descriptor address. */
/* 0x6D0 */
union tx_des_addr {
	/* Define the struct bits */
	struct {
		/* [ 31 ] packet sending buffer is released. Low level is valid. */
		unsigned int tx_bd_rel : 1;
		/* [ 30 ] is reserved. */
		unsigned int reserved_42 : 1;
		/* [ 29..0 ] Transmit Descriptor address [ 35:6 ]. */
		unsigned int tx_bd_addr : 30;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union MC_PPE_CURR_BUF_CNT_U */
/* PPE_CURR_BUF_CNT. 0xA200~0xA27C are the number of cached pool_0~pool_31 buffer pointer */
/* 0xA200+pool_num*0x4 */
union curr_buf_cnt  {
	/* Define the struct bits */
	struct {
		/* [ 31..12 ] are reserved. */
		unsigned int reserved_50 : 20;
		/* [ 11..0 ] Number of buffered in the pool */
		unsigned int buf_cnt : 12;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union ppe_inten */
/* PPE_INTEN is the interrupt enable register. */
/* 0x700 */
union ppe_inten {
	/* Define the struct bits */
	struct {
		/* [ 31..23 ] reserved */
		unsigned int reserved_44 : 9;
		/* [ 22 ] Illegal VMID access interrupt enable registers: 0: disable 1: enable. */
		unsigned int vmid_err_acc_int_msk : 1;
		/* [ 21 ] Add POE, write POE true full interrupt enable register: 0: disable 1: enable. */
		unsigned int poe_rel_full_int_msk : 1;
		/* [ 20 ] The POE,POE returns the VMID mismatch interrupt enable register: 0: disable 1: enable. */
		unsigned int poe_vmid_err_int_msk : 1;
		/* [ 19 ] Add POE, write POE filler full interrupt enable register: 0: disable 1: enable. */
		unsigned int add_poe_int_msk : 1;
		/* [ 18 ] Receiving release BMU failure interrupt enable register: 0: disable 1: enable. */
		unsigned int rx_rel_bmu_int_msk : 1;
		/* [ 17 ] The descriptor state machine heartbeat detection timeout interrupt enable register:
		 * 0: disable 1: enable.
		 */
		unsigned int wpd_st_heat_int_msk : 1;
		/* [ 16 ] Resolving the state machine heartbeat detection timeout interrupt enable register:
		 * 0: disable 1: enable.
		 */
		unsigned int pa_st_heat_int_msk : 1;
		/* [ 15 ] receive state machine heartbeat detection timeout interrupt enable register
		 * 0: disable 1: enable.
		 */
		unsigned int rx_st_heat_int_msk : 1;
		/* Tx state machine  [ 14 ] heartbeat detection timeout interrupt enable register
		 * 0: disable 1: enable.
		 */
		unsigned int tx_st_heat_int_msk : 1;
		/* [ 13 ] TX descriptor address FIFO overflow interrupt enable register: 0: disable 1: enable. */
		unsigned int tx_bd_addr_fifo_int_msk : 1;
		/* [12] GE FIFO exception interrupt enable register 0: disable 1: enable. */
		unsigned int ge_fifo_int_msk : 1;
		/* [ 11 ] write DDR bus error interrupt enable register 0: disable 1: enable. */
		unsigned int ddr_rw_int_msk : 1;
		/* [ 10 ] received packets meet the configuration conditions interrupt
		 * enable register (reference address is 0x538 description): 0: disable 1: enable.
		 */
		unsigned int rx_pkt_int_msk : 1;
		/* [ 9 ] received packets discarded due to first-level low interrupt enable register:
		 * 0: disable 1: enable.
		 */
		unsigned int rx_low_qos_int_msk : 1;
		/* [ 8 ] received packets discarded due to lack of cache interrupt enable register:
		 * 0: disable 1: enable.
		 */
		unsigned int rx_no_buf_int_msk : 1;
		/* [ 7 ] RX packets discarded because of FIFO full interrupt enable register: 0: disable 1: enable. */
		unsigned int rx_drop_int_msk : 1;
		/* [ 6 ] send packets discarded because of FIFO empty interrupt enable register:
		 * 0: disable 1: enable.
		 */
		unsigned int tx_drop_int_msk : 1;
		/* [ 5 ] The BMU release failure interrupt enable register: 0: disable 1: enable. */
		unsigned int tx_rel_bmu_int_msk : 1;
		/* [4] VMID SRAM parity check error interrupt enable register is as follows: 0: disable 1: enable. */
		unsigned int vmid_sram_par_int_msk : 1;
		/* [ 3 ] The packet descriptors SRAM is 2bit ECC error interrupt enable register:
		 * 0: disable 1: enable.
		 */
		unsigned int tx_bd_sram_ecc_2b_int_msk : 1;
		/* [ 2 ] The packet descriptors SRAM is 1bit ECC error interrupt enable register:
		 * 0: disable 1: enable.
		 */
		unsigned int tx_bd_sram_ecc_1b_int_msk : 1;
		/* [ 1 ] The packet SRAM parity check error interrupt enable register is as follows:
		 * 0: disable 1: enable.
		 */
		unsigned int tx_sram_par_int_msk : 1;
		/* [ 0 ] packet receiving SRAM ECC error interrupt enable register is as follows:
		 * 0: disable 1: enable.
		 */
		unsigned int rx_sram_par_int_msk : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union ppe_rint */
/* PPE_RINT is the raw interrupt register. */
/* 0x704 */
union ppe_rint {
	/* Define the struct bits */
	struct {
		/* [ 31..23 ] reserved */
		unsigned int reserved_46 : 9;
		/* [ 22 ] Illegal VMID register access raw interrupt register */
		unsigned int vmid_err_acc_int_r : 1;
		/* [ 21 ] Add POE, write POE true full raw interrupt */
		unsigned int poe_rel_full_int_r : 1;
		/* [ 20 ] The POE,POE returns the VMID not match raw interrupt register */
		unsigned int poe_vmid_err_int_r : 1;
		/* [ 19 ] Add POE, write POE filler full raw interrupt */
		unsigned int add_poe_int_r : 1;
		/* [ 18 ] Receiving Failed to release BMU raw interrupt register */
		unsigned int rx_rel_bmu_int_r : 1;
		/* [ 17 ] The descriptor state machine heartbeat detection raw interrupt register */
		unsigned int wpd_st_heat_int_r : 1;
		/* [ 16 ] Resolving the state machine heartbeat detection timeout raw interrupt register */
		unsigned int pa_st_heat_int_r : 1;
		/* [ 15 ] receive state machine heartbeat detection timeout raw interrupt register */
		unsigned int rx_st_heat_int_r : 1;
		/* Tx state machine  [ 14 ] heartbeat detection timeout raw interrupt register */
		unsigned int tx_st_heat_int_r : 1;
		/* [ 13 ] TX descriptor address FIFO overflow raw interrupt register */
		unsigned int tx_bd_addr_fifo_int_r : 1;
		/* [12] GE FIFO error raw interrupt register */
		unsigned int ge_fifo_int_r : 1;
		/* [ 11 ] write DDR bus error raw interrupt register */
		unsigned int ddr_rw_int_r : 1;
		/* [ 10 ] received packets meet configuration requirements of
		 * the raw interrupt register (reference address is 0x538 description)
		 */
		unsigned int rx_pkt_int_r : 1;
		/* [ 9 ] received packets discarded due to first-level low raw interrupt register */
		unsigned int rx_low_qos_int_r : 1;
		/* [ 8 ] received packets discarded due to lack of cache raw interrupt register */
		unsigned int rx_no_buf_int_r : 1;
		/* [ 7 ] Receiving packets discarded because of FIFO full raw interrupt register */
		unsigned int rx_drop_int_r : 1;
		/* [ 6 ] send packets discarded because of FIFO empty raw interrupt register */
		unsigned int tx_drop_int_r : 1;
		/* [ 5 ] The Failed to release BMU raw interrupt register */
		unsigned int tx_rel_bmu_int_r : 1;
		/* [4] VMID SRAM parity check error occurs raw interrupt register */
		unsigned int vmid_sram_par_int_r : 1;
		/* [ 3 ] The packet descriptors SRAM is 2bit ECC error raw interrupt register. */
		unsigned int tx_bd_sram_ecc_2b_int_r : 1;
		/* [ 2 ] The packet descriptors SRAM is 1bit ECC error raw interrupt register. */
		unsigned int tx_bd_sram_ecc_1b_int_r : 1;
		/* [ 1 ] The packet SRAM parity error occurs raw interrupt register */
		unsigned int tx_sram_par_int_r : 1;
		/* [ 0 ] packet receiving SRAM ECC error occurs raw interrupt register */
		unsigned int rx_sram_par_int_r : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union ppe_intsts */
/* PPE_INTSTS is the interrupt status register. */
/* 0x708 */
union ppe_intsts {
	/* Define the struct bits */
	struct {
		/* [ 31..23 ] reserved */
		unsigned int reserved_47 : 9;
		/* [ 22 ] Illegal VMID register access interrupt status register */
		unsigned int vmid_err_acc_int_sts : 1;
		/* [ 21 ] Add POE, write POE Telepresence interrupt status register */
		unsigned int poe_rel_full_int_sts : 1;
		/* [ 20 ] The POE,POE returns the VMID mismatch interrupt status register */
		unsigned int poe_vmid_err_int_sts : 1;
		/* [ 19 ] Add POE, write POE filler full interrupt status register */
		unsigned int add_poe_int_sts : 1;
		/* [ 18 ] Receiving Failed to release BMU interrupt status register */
		unsigned int rx_rel_bmu_int_sts : 1;
		/* [ 17 ] The descriptor state machine heartbeat detection timeout interrupt status register */
		unsigned int wpd_st_heat_int_sts : 1;
		/* [ 16 ] Resolving the state machine heartbeat detection timeout interrupt status register */
		unsigned int pa_st_heat_int_sts : 1;
		/* [ 15 ] receive state machine heartbeat detection timeout interrupt status register */
		unsigned int rx_st_heat_int_sts : 1;
		/* Tx state machine  [ 14 ] heartbeat detection timeout interrupt status register */
		unsigned int tx_st_heat_int_sts : 1;
		/* [ 13 ] TX descriptor address FIFO overflow interrupt status register */
		unsigned int tx_bd_addr_fifo_int_sts : 1;
		/* [12] GE FIFO exception interrupt status register */
		unsigned int ge_fifo_int_sts : 1;
		/* [ 11 ] write DDR bus error interrupt status register */
		unsigned int ddr_rw_int_sts : 1;
		/* [ 10 ] received packets meet the configuration conditions interrupt
		 * status register (reference address is 0x538 description)
		 */
		unsigned int rx_pkt_int_sts : 1;
		/* [ 9 ] received packets discarded due to first-level low interrupt status register */
		unsigned int rx_low_qos_int_sts : 1;
		/* [ 8 ] received packets discarded due to lack of cache interrupt status register */
		unsigned int rx_no_buf_int_sts : 1;
		/* [ 7 ] Receiving packets discarded because of FIFO full interrupt status register */
		unsigned int rx_drop_int_sts : 1;
		/* [ 6 ] send packets discarded because of FIFO empty interrupt status register */
		unsigned int tx_drop_int_sts : 1;
		/* [ 5 ] The BMU release failure interrupt status register */
		unsigned int tx_rel_bmu_int_sts : 1;
		/* The [4] VMID of the SRAM parity check error interrupt status register */
		unsigned int vmid_sram_par_int_sts : 1;
		/* [ 3 ] The packet descriptors SRAM is 2bit ECC error interrupt status register */
		unsigned int tx_bd_sram_ecc_2b_int_sts : 1;
		/* [ 2 ] The packet descriptors SRAM is 1bit ECC error interrupt status register */
		unsigned int tx_bd_sram_ecc_1b_int_sts : 1;
		/* [ 1 ] The packet is SRAM parity check error interrupt status register */
		unsigned int tx_sram_par_int_sts : 1;
		/* [ 0 ] packet receiving SRAM ECC error occurs interrupt status register */
		unsigned int rx_sram_par_int_sts : 1;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union rx_pkt_cfg */
/* PPE_CFG_RX_PKT_INT is received from a specified number or receive packets timeout interrupt is reported. */
/* 0x740 */
union rx_pkt_cfg {
	/* Define the struct bits */
	struct {
		/* [ 31..12 ] are reserved. */
		unsigned int reserved_48 : 20;
		/* Interruption packets received  [ 11..6 ] maximum number. That is, when the number of
		 * received packets is greater than the configured value, an interrupt is
		 * reported rx_pkt_int_r valid (delete rx_pkt_int_r. This configuration is valid only when
		 */
		unsigned int cf_intrpt_pkt : 6;
		/* [ 5..0 ] Receiving time limit. After receiving the packets exceeds the set value,
		 * the RSCG is considered as RX timeout.
		 */
		unsigned int cf_intrpt_time : 6;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

/* Define the union cff_data_num */
/* PPE_CURR_DATA_NUM is the configuration FIFO data count register. */
/* 0x8C8 */
union cff_data_num {
	/* Define the struct bits */
	struct {
		/* [ 31..14 ] cannot be configured. */
		unsigned int reserved_70 : 18;
		/* [ 13..7 ] Number of Transmit Descriptor address
		 * in FIFO (sends 0x0580+cpu_num*0x4 added descriptors)
		 */
		unsigned int tx_cfg_num_cpu : 7;
		/* [ 6..0 ] Number of Transmit Descriptor address in FIFO (sends 0x420 added descriptors) */
		unsigned int tx_cfg_num : 7;
	} bits;

	/* Define an unsigned member */
	unsigned int    u32;
};

#endif /* GMAC_PPE_REG_H */
